1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a level shifting circuit for a power device preventing a malfunction resulting from a dv/dt transient signal.
2. Description of the Background Art
FIG. 36 shows the structure of a level shifting circuit 90 for a conventional power device. The structure shown in FIG. 36 is disclosed in Japanese Patent Laying-Open Gazette No. 9-200017 (1997).
Referring to FIG. 36, power devices 12 and 13 such as IGBTs (insulated gate bipolar transistors) are totem-pole-connected between a positive electrode and a negative electrode (ground potential GND) of a power source PS, to form a half-bridge power device. Freewheel diodes D1 and D2 are connected with the power devices 12 and 13 respectively in an antiparallel manner. A load (an inductive load such as a motor) 14 is connected to a node N1 between the power devices 12 and 13.
Referring to FIG. 36, the power device 12, switching between a reference potential defined by the potential of the node N1 between the power devices 12 and 13 and a power supply potential supplied by the power source PS, is referred to as a high-potential side power device.
The power device 13, switching between a reference potential defined by the ground potential and the potential of the node N1, is referred to as a low-potential side power device.
Therefore, the level shifting circuit 90 shown in FIG. 36 is divided into a high-potential side power device driving circuit HD and a low-potential side power device driving circuit LD.
The high-potential side power device driving circuit HD has NMOS transistors 24 and 25 serially connected between a positive electrode and a negative electrode of a high-potential side power source 10 for the driving circuit HD, and switches the power device 12 by complementarily turning on/off the NMOS transistors 24 and 25. The negative electrode of the high-potential side power source 10 is connected to the node N1. The voltage of the node between the NMOS transistors 24 and 25 is referred to as a high-potential side output voltage HO.
The high-potential side power device driving circuit HD has a pulse generation circuit 3 generating pulsing ON and OFF signals in response to positive level transition and negative level transition of a pulsing input signal S1, supplied from an externally provided microcomputer or the like, generated with reference to the ground potential for driving the NMOS transistors 24 and 25.
Two outputs of the pulse generation circuit 3 are connected to the gate electrodes of high withstand voltage N-channel field-effect transistors (hereinafter referred to as HNMOS transistors) 4 and 5 which are level shifting transistors. The ON and OFF signals are supplied to the gate electrodes of the HNMOS transistors 4 and 5 respectively.
The drain electrodes of the HNMOS transistors 4 and 5 are connected to first ends of resistors 29 and 30 as well as to inputs of inverter circuits 6 and 7 respectively.
Outputs of the inverter circuits 6 and 7 are connected to an input of a protective circuit 8 having an output connected to set and reset inputs of an SR flip-flop circuit 9. The protective circuit 8, serving as a filter circuit for preventing the SR flip-flop circuit 9 from a malfunction, is formed by a logic gate. The protective circuit 8 may also be referred to as a filter circuit 8.
A Q output of the SR flip-flop circuit 9 is connected to the gate electrode of the NMOS transistor 24 as well as to an input of an inverter circuit 23 having an output connected to the gate electrode of the NMOS transistor 25.
Second ends of the resistors 29 and 30 are connected to the drain electrode of the NMOS transistor 24, i.e., the positive electrode (the voltage thereof is referred to as a high-potential side floating power supply absolute voltage VB) of the high-potential side power source 10. The source electrode of the NMOS transistor 24, i.e., the negative electrode (the voltage thereof is referred to as a high-potential side floating power supply offset voltage VS) of the high-potential side power source 10 is connected to anodes of diodes 21 and 22 having cathodes connected to the drain electrodes of the HNMOS transistors 4 and 5 respectively.
The low-potential side power device driving circuit LD has NMOS transistors 27 and 28 serially connected between a positive electrode (the voltage thereof is referred to as a low potential side fixed power supply voltage VCC) and a negative electrode (ground potential) of a low-potential side power source 11 for the driving circuit LD, and switches the power device 13 by complementarily turning on/off the NMOS transistors 27 and 28. The voltage of the node between the NMOS transistors 27 and 28 is referred to as a low potential side output voltage LO, whose change defines a control signal S7 for controlling the power device 13. The NMOS transistor 27 is controlled by an externally supplied input signal S0, while the NMOS transistor 28 is controlled by a signal obtained by inverting the input signal S0 by an inverter circuit 26.
Operations of the level shifting circuit 90 are now described with reference to a timing chart shown in FIG. 37.
Referring to FIG. 37, the pulse generation circuit 3 successively generates pulses as ON and OFF signals S2 and S3 respectively in response to positive level transition and negative level transition of the externally supplied pulsing input signal S1.
First, a pulse signal making transition to a high potential is supplied as the OFF signal S3. At this time, the OFF signal S3 is at a low potential, and the HNMOS transistor 4 is turned on by the ON signal S2. The HNMOS transistor 5 is in an OFF state.
Thus, the resistor 29 connected to the HNMOS transistor 4 causes a voltage drop, for inputting a low-level signal in the inverter circuit 6. On the other hand, the resistor 30 connected to the HNMOS transistor 5 causes no voltage drop, for continuously inputting a high-level signal in the inverter circuit 7. Thus, the inverter circuit 6 outputs a pulse signal S4 making transition to a high level, while the inverter 7 outputs a signal S5 remaining low.
The protective circuit 8 receiving the output signals S4 and S5 from the inverter circuits 6 and 7 outputs a pulse signal S6 and a low-level signal S7 in correspondence to the output signals S4 and S5 from the inverter circuits 6 and 7 respectively.
Also when a pulse signal making transition to a high potential is supplied as the OFF signal S3, the level shifting circuit 90 performs operations similar to the above so that the protective circuit 8 outputs a pulse signal S7 and a low-level signal S6 in correspondence to the output signals S5 and S4 from the inverter circuits 7 and 6 respectively.
Consequently, an output signal S8 from the SR flip-flop circuit 9 goes high at a timing supplied with the ON signal S2 and goes low at a timing supplied with the OFF signal S3. A similar control signal S9 for the power device 12 is obtained by complementarily turning on/off the NMOS transistors 24 and 25.
Depending on the switching state of the half-bridge power device formed by the power devices 12 and 13, a dv/dt transient signal is disadvantageously generated in a line connecting the node N1 and the anodes of the diodes 21 and 22.
When the dv/dt transient signal is generated, a dv/dt current obtained by integrating drain-to-source parasitic electrostatic capacitances of the HNMOS transistors 4 and 5 and the dv/dt transient signal simultaneously flows to the HNMOS transistors 4 and 5.
Thus, it follows that error pulses P1 and P2 resulting from the dv/dt transient signal are simultaneously supplied as the signals S2 and S3 in place of the ON and OFF signals, while the protective circuit 8 is formed to prevent the SR flip-flop circuit 9 from such simultaneous signal inputs.
However, while the protective circuit 8 functions as a filter when the error pulses P1 ad P2 resulting from the dv/dt transient signal are simultaneously supplied as the signals S2 and S3, pulse signals P11 and P12 having widths responsive to time difference are supplied to the output signals S6 and S7 of the protective circuit 8 when the error pulses P1 and P2 resulting from the dv/dt transient signal are supplied with slight time difference due to dispersion of the element characteristics of the HNMOS transistors 4 and 5, leading to a malfunction bringing the power device 12 into an ON or OFF state by the pulse signals P11 and P12.
This malfunction of the power device 12 is maintained until a normal ON or OFF signal is subsequently supplied, and the power devices 12 and 13 may be shorted to cause inconvenience as the case may be.
An object of the present invention is to provide a level shifting circuit capable of preventing a power device from a malfunction even if a dv/dt transient signal is supplied with time difference.
According to a first aspect, a semiconductor device driving/controlling first and second switching devices serially connected with each other and interposed between a high main power supply potential and a low main power supply potential includes a control part, a pulse generation part and a level shifting part.
That is, the control part controls conduction/non-conduction of a high-potential side switching device of either the first or second switching device.
The pulse generation part generates first and second iterative pulse signals in correspondence to first and second states of a first input signal having the first state indicating conduction of the high-potential side switching device and the second state indicating non-conduction of the high-potential side switching device.
The level shifting part level-shifts the first and second iterative pulse signals to a higher potential side for obtaining first and second level-shifted iterative pulse signals respectively, and the control part outputs a control signal rendering the high-potential side switching device conductive or non-conductive on the basis of the first and second level-shifted iterative pulse signals.
The first and second iterative pulse signals having pulses of a constant cycle are supplied as ON and OFF signals in correspondence to the first input signal so that first and second level shifting semiconductor elements are cyclically turned on for level-shifting the ON and OFF signals to high-potential sides and converting the same to the first and second level-shifted iterative pulse signals. Even if an error pulse resulting from a dv/dt transient signal is supplied to the first and second iterative pulse signals for setting the control part, therefore, this period sustains only until a normal pulse is supplied as the OFF signal. Therefore, a period when both of the first and second switching devices are in ON states is limited to that corresponding to the cycle of the first and second iterative pulse signals at the maximum followed by normal control, whereby the first and second switching devices can be prevented from being simultaneously turned on and inconveniently shorted.
In the semiconductor device, the pulse generation part preferably includes a clock signal generation part generating a clock signal, an iterative pulse generation part, a first one-shot pulse generation circuit, a second one-shot pulse generation circuit, a first logic circuit and a second logic circuit.
That is, the iterative pulse generation part receives the clock signal and the first input signal and outputs the clock signal as a first signal only in a period when the first input signal is in the first state while outputting the clock signal as a second signal only in a period when the first input signal is in the second state.
The first one-shot pulse generation circuit receives the first input signal and outputs a third signal having a pulse synchronized with transition of the first input signal to the first state in each cycle of the first input signal.
The second one-shot pulse generation circuit receives an inverted signal of the first input signal and outputs a fourth signal having a pulse synchronized with transition of the first input signal to the second state in each cycle of the first input signal.
The first logic circuit receives the first and third signals, operates the OR of the signals and outputs the same as the first iterative pulse signal.
The second logic circuit receives the second and fourth signals, operates the OR of the signals and outputs the same as the second iterative signal.
The semiconductor device uses the signals obtained by operating the ORs of the respective ones of the first and second signals output from the iterative pulse generation part and the third and fourth signals output from the first and second one-shot pulse generation circuits as the first and second iterative pulse signals, whereby the first and second iterative pulse signals are synchronized with the first input signal so that a time delay resulting from signal displacement can be eliminated between the first input signal and a control signal for the high-potential side switching device, i.e., between an input and an output, for preventing the high-potential side switching device from reduction in response speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.